MUNICH — Electroglas Inc. today at the Semicon Europa trade show here introduced a new test-handling solution for devices in wafer-level packages, unpackaged known-good die products, thin wafers, ...
TOKYO–Japan's Tokyo Electron Ltd. (TEL) announced Monday (April 12) that it will begin sales of a test handler that supports wafer-level packages and known-good die (KGD) products. Current process ...
The high power density in turn produces large thermal gradients, with the low to max temperature changes increasing ...
FREMONT, CA / ACCESSWIRE / April 2, 2024 / Aehr Test Systems (NASDAQ:AEHR), a worldwide supplier of semiconductor test and burn-in equipment, today announced it has received an initial customer order ...
SAN JOSE, Calif.--(BUSINESS WIRE)--July 15, 2004--Electroglas, Inc. (Nasdaq:EGLS), a leading supplier of wafer probing and test handling solutions for the semiconductor industry, today announced that ...
FREMONT, Calif., Nov. 09, 2020 (GLOBE NEWSWIRE) -- Aehr Test Systems (NASDAQ: AEHR), a worldwide supplier of semiconductor test and reliability qualification equipment, will be showcasing its FOX-P™ ...
This equipment is also set up for 200 mm wafer frame probing of a wide range of semiconductor devices. As a pioneer in developing and deploying application-specific test solutions for MEMS devices, ...
Semiconductor testing has traditionally functioned as a stable screening step in the manufacturing flow so that failing devices can be identified and separated prior to packaging. Test infrastructure ...
FREMONT, Calif., Oct. 06, 2022 (GLOBE NEWSWIRE) -- Aehr Test Systems (AEHR), a worldwide supplier of semiconductor test and reliability qualification equipment, today announced it has released two new ...
FREMONT, CA / ACCESSWIRE / January 7, 2025 / Aehr Test Systems (AEHR), a worldwide supplier of semiconductor test and burn-in equipment, today announced it has received an initial production order ...
In a heterogeneous integrated system, the impact of composite yield fallout due to a single chiplet is creating new performance imperatives for wafer test in terms of test complexity and coverage.
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