EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. — Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...

Evolving Hardware Languages In The Age Of AI And LLMs

This is not about replacing Verilog. It’s about evolving the hardware development stack so engineers can operate at the level of intent, not just implementation.
Design-Reuse

Siemens launches Tessent tool for Verilog and RTL design for test

The Tessent RTL Pro enables analysis and insertion of a large majority of their DFT logic very early in the design flow, performing quick synthesis and then running ATPG (automatic test pattern ...
Design-Reuse

Bluespec Updates ESL Synthesis Toolset; Offers Improved Verilog RTL Output for Practical IP Delivery Vehicle

WALTHAM, Mass.--May 11, 2006--Bluespec Inc. today released the latest version of its electronic system level (ESL) Synthesis software, offering a practical delivery vehicle for intellectual property ...